CAD for Hardware Security (硬體安全的CAD)

本書概述了當前硬體安全問題的概況，並強調如何使用電腦輔助設計（CAD）工具有效解決這些問題。作者包括CAD開發人員、IP開發人員、SOC設計師以及SOC驗證專家。通過積極的對策和各種CAD解決方案的有效結合，讀者將全面了解SOC安全漏洞以及如何克服這些漏洞。

Farimah Farahmandi is an assistant professor in the Department of Electrical and Computer Engineering (ECE) and the associate director of Edaptive Computing Inc., Transition Center (ECI-TC), and Florida Institue for Cybersecurity (FICS) at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering (CISE) at the University of Florida, 2018. Her research interests include hardware security verification, formal methods, fault-injection attack analysis, side-channel leakage assessment, information leakage, secure physical design, secure supply chain of microelectronics, and post-silicon validation and debug. Her research has resulted in five books, nine book chapters, and several publications in premier ACM/IEEE journals and conferences including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards including 2022 Semiconductor Research Corporation Young Faculty Award and the 2022 ECE Research Excellence Award at UF. She is also the recipient of four best paper nominations from IEEE/ACM ASPDAC and IEEE/ACM DATE as well as IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, and DAC Richard Newton Young Student Fellowship. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She also has served on many technical program committees as well as organizing committees of premier ACM and IEEE conferences. Currently, she is the program chair of IEEE HOST 2023. Her research has been sponsored by SRC, DARPA, AFRL, DoD, ONR, Analog Devices, ANSYS, Synopsys, and Cisco. She is a member of IEEE and ACM.

M Sazadur Rahman a Security Assurance architecture Engineer at Intel Corporation. He earned his M.Sc. and Ph.D. degree under the supervision of Prof. Mark Tehranipoor from University ofFlorida in 2022. He got his B.Sc. in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology in 2014. He worked as a design engineer in different fabless semiconductor companies from 2014 to 2017 in industrial scale 28nm and 14nm custom ICs. His research has resulted in one book, multiple patents, and several peer-reviewed publications in premier ACM/IEEE journals and conferences, including the Design Automation Conference (DAC), Design automation and test in Europe (DATE), IEEE International Test Conference (ITC), IEEE Hardware Oriented Security and Trust (HOST), IEEE VLSI Test symposium (VTS), Elsevier Integration, ACM Transactions on Design Automation of Electronic Systems (TODAES), etc. He has multiple internship experiences at Intel Corporation, where he performed FIPS 140-3 security certification and developed an automated threat model review tool for different adversary models. His research interest includes IP protection and authentication, logic locking, security estimation, and CAD for security.
Sree Ranjani Rajendran is a postdoctoral associate in the Department of Electrical and Computer Engineering at the University of Florida. She received her Ph.D. from the Department of Electronics and Communication Engineering at the Amrita Vishwa Vidyapeetham in 2019. She received her B.E. and M.E. from the Department of Electronics and Communication Engineering at Anna University, sIndia, in 2007 and 2012.Her research interests include hardware security verification and validation of System-on-Chips. Her research has been published in premier ACM/IEEE journals and conferences, including IEEE Transactions on Emerging Topics in Computing, Journal of Cryptographic Engineering, ACM Workshop on Attacks and Solutions in Hardware Security, International Conference on VLSI Design & The International Conference on Embedded Design, and Design Automation and Test in Europe (DATE). She is a member of IEEE andThe Test Technology Technical Community (TTTC). Her research has been awarded in IEEE Young Women Research Grant Award, 28th IEEE Asian Test Symposium (ATS), 2019.

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the the University of Florida. He served as the founding Director for Florida Institute for Cybersecurity (FICS) Research from 2015-2022, and currently serving as Director for Edaptive Computing Inc. Transition Center (ECI-TC), Co-director for the AFOSR/AFRL Center of Excellence on Enabling Cyber Defense in Analog and Mixed Signal Domain (CYAN), and Co-Director for the National Microelectronic Security Training Center (MEST). He also served as the Associate Chair for Research and Strategic Initiatives for the ECE Department from 2017-2019 and the Program Director of Cybersecurity in the Herbert Wertheim College of Engineeringfrom 2019-2022. His current research projects include hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. Dr. Tehranipoor has published numerous journal articles and refereed conference papers and has delivered 220+ invited talks and keynote addresses. In addition, he has 19 patents issued, 22 pending invention disclosures, and has published 16 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies. Dr. Tehranipoor is a Fellow of IEEE, a Fellow of ACM, a Fellow of the National Academy of Engineering (NAI), a Golden Core Member of IEEE Computer Society, and a Member of ACM SIGDA. He is also a member of the Connecticut Academy of Sciences and Engineering (CASE). He is a recipient of 17 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 AFOSR MURI award on Nanoscale Security, the 2008 IEEE Computer Society (CS) Meritorious Service award, the 2012 and 2017 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2018 IEEE HOST Hall of Fame Member, the 2009 and 2014 UConn ECE Research Excellence award, the 2012 UConn SOE Outstanding Faculty Advisor award, the 2016 UF College of Engineering Excellence in Leadership award, the 2016 UF ECE Research Excellence Award, the 2020 UF's College of Engineering Teacher/Scholar of the year award, the 2020 UF Innovation of the Year Award, and the 2022 IEEE CS TTTC Bob Madge Innovation Award. He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, ACM JETC, and IEEE Computer Society Computing Now. He served as Program Chair of the 2019 International Test Conference (ITC), Vice-program Chair of the 2018 ITC, Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, 2016 IEEE International Verification and Security Workshop (IVSW), Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011, General Chair for 2008-2009, and 2021-2022 IEEE HOST, and General Chair for 2019-2021 IEEE PAINE Conference. Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut.

Farimah Farahmandi是佛羅里達大學電機與電腦工程系（ECE）的助理教授，也是Edaptive Computing Inc.轉型中心（ECI-TC）和佛羅里達資訊安全研究所（FICS）的副主任。她於2018年從佛羅里達大學計算機與資訊科學工程系（CISE）獲得博士學位。她的研究興趣包括硬體安全驗證、形式方法、故障注入攻擊分析、側信道洩漏評估、信息洩漏、安全物理設計、微電子安全供應鏈和後硅驗證和調試。她的研究成果包括五本書、九個書章和多篇發表在頂級ACM/IEEE期刊和會議上的文章，包括IEEE Transactions on Computers、IEEE Transactions on CAD、Design Automation Conference（DAC）和Design Automation and Test in Europe（DATE）。她的研究獲得了多個獎項的認可，包括2022年半導體研究公司青年教師獎和佛羅里達大學2022年ECE研究卓越獎。她還獲得了來自IEEE/ACM ASPDAC和IEEE/ACM DATE的四個最佳論文提名，以及IEEE系統驗證和調試技術委員會學生研究獎、Gartner Group Info-Tech獎學金和DAC Richard Newton青年學生研究獎。她目前擔任IET Computers & Digital Techniques的副編輯。她還曾擔任過許多頂級ACM和IEEE會議的技術程序委員會和組織委員會成員。目前，她是IEEE HOST 2023的程序主席。她的研究得到了SRC、DARPA、AFRL、DoD、ONR、Analog Devices、ANSYS、Synopsys和Cisco的資助。她是IEEE和ACM的成員。

M Sazadur Rahman是英特爾公司的安全保證架構工程師。他在2022年在佛羅里達大學師從Mark Tehranipoor教授獲得了碩士和博士學位。他於2014年在孟加拉工程與技術大學獲得電氣與電子工程學士學位。他在2014年至2017年期間曾在不同的無廠半導體公司擔任設計工程師，從事工業規模的28nm和14nm定制集成電路設計。他的研究成果包括一本書、多個專利和多篇發表在頂級ACM/IEEE期刊和會議上的同行評審文章，包括Design Automation Conference（DAC）、Design automation and test in Europe（DATE）、IEEE International Test Conference（ITC）、IEEE Hardware Oriented Security and Trust（HOST）、IEEE VLSI Test symposium（VTS）、Elsevier Integration、ACM Transactions on Design Automation of Electronic Systems（TODAES）等。他在英特爾公司有多次實習經驗，曾進行FIPS 140-3安全認證並為不同的對手模型開發了自動化威脅模型審查工具。他的研究興趣包括IP保護和驗證、邏輯鎖定、安全估計和安全CAD。

Sree Ranjani Rajendran是佛羅里達大學電機與電腦工程系的博士後研究員。她於2019年從Amrita Vishwa Vidyapeetham的電子與通信工程系獲得博士學位。她於2007年和2012年分別在Anna University的電子與通信工程系獲得學士和碩士學位。她的研究興趣包括硬體安全驗證和系統單晶片的驗證。她的研究成果發表在頂級ACM/IEEE期刊和會議上，包括IEEE Transactions on Emerging Topics in Computing、Journal of Cryptographic Engineering、ACM Workshop on Attacks and Solutions in Hardware Security、International Conference on VLSI Design & The International Conference on Embedded Design和Design Automation and Test in Europe（DATE）。她是IEEE和The Test Technology Tec的成員。