This book focuses on neuromorphic computing principles and organization and how to build fault-tolerant scalable hardware for large and medium scale spiking neural networks with learning capabilities. In addition, the book describes in a comprehensive way the organization and how to design a spike-based neuromorphic system to perform network of spiking neurons communication, computing, and adaptive learning for emerging AI applications. The book begins with an overview of neuromorphic computing systems and explores the fundamental concepts of artificial neural networks. Next, we discuss artificial neurons and how they have evolved in their representation of biological neuronal dynamics. Afterward, we discuss implementing these neural networks in neuron models, storage technologies, inter-neuron communication networks, learning, and various design approaches. Then, comes the fundamental design principle to build an efficient neuromorphic system in hardware. The challenges that need to be solved toward building a spiking neural network architecture with many synapses are discussed. Learning in neuromorphic computing systems and the major emerging memory technologies that promise neuromorphic computing are then given.
A particular chapter of this book is dedicated to the circuits and architectures used for communication in neuromorphic systems. In particular, the Network-on-Chip fabric is introduced for receiving and transmitting spikes following the Address Event Representation (AER) protocol and the memory accessing method. In addition, the interconnect design principle is covered to help understand the overall concept of on-chip and off-chip communication. Advanced on-chip interconnect technologies, including si-photonic three-dimensional interconnects and fault-tolerant routing algorithms, are also given. The book also covers the main threats of reliability and discusses several recovery methods for multicore neuromorphic systems. This is important for reliable processing in several embedded neuromorphic applications. A reconfigurable design approach that supports multiple target applications via dynamic reconfigurability, network topology independence, and network expandability is also described in the subsequent chapters. The book ends with a case study about a real hardware-software design of a reliable three-dimensional digital neuromorphic processor geared explicitly toward the 3D-ICs biological brain's three-dimensional structure. The platform enables high integration density and slight spike delay of spiking networks and features a scalable design. We present methods for fault detection and recovery in a neuromorphic system as well.
Neuromorphic Computing Principles and Organization is an excellent resource for researchers, scientists, graduate students, and hardware-software engineers dealing with the ever-increasing demands on fault-tolerance, scalability, and low power consumption. It is also an excellent resource for teaching advanced undergraduate and graduate students about the fundamentals concepts, organization, and actual hardware-software design of reliable neuromorphic systems with learning and fault-tolerance capabilities.
本書專注於神經形態計算的原則與組織,以及如何為具有學習能力的大型和中型脈衝神經網絡構建容錯可擴展的硬體。此外,本書全面描述了如何設計基於脈衝的神經形態系統,以執行脈衝神經元之間的通信、計算和自適應學習,以應對新興的人工智慧應用。書中首先概述了神經形態計算系統,並探討了人工神經網絡的基本概念。接著,我們討論了人工神經元及其在生物神經動力學表徵上的演變。隨後,我們討論了在神經元模型、儲存技術、神經元間通信網絡、學習及各種設計方法中實現這些神經網絡的方式。然後,介紹了構建高效神經形態系統的基本設計原則。書中還討論了在構建具有多個突觸的脈衝神經網絡架構時需要解決的挑戰。接著,介紹了神經形態計算系統中的學習以及承諾神經形態計算的主要新興記憶技術。
本書的一個特定章節專門介紹了用於神經形態系統通信的電路和架構。特別是,介紹了用於接收和傳輸脈衝的片上網絡(Network-on-Chip)架構,遵循地址事件表示(Address Event Representation, AER)協議和記憶體存取方法。此外,還涵蓋了互連設計原則,以幫助理解片上和片外通信的整體概念。書中還介紹了先進的片上互連技術,包括矽光子三維互連和容錯路由算法。本書還涵蓋了可靠性面臨的主要威脅,並討論了多核神經形態系統的幾種恢復方法。這對於多個嵌入式神經形態應用中的可靠處理至關重要。隨後的章節中還描述了一種可重構設計方法,支持通過動態重構、網絡拓撲獨立性和網絡擴展性來滿足多個目標應用的需求。本書以一個案例研究結束,該研究關於一個可靠的三維數位神經形態處理器的實際硬體-軟體設計,專門針對3D-IC的生物大腦三維結構。該平台實現了高集成密度和脈衝網絡的輕微脈衝延遲,並具備可擴展的設計。我們還提出了在神經形態系統中進行故障檢測和恢復的方法。
《神經形態計算原則與組織》是研究人員、科學家、研究生和硬體-軟體工程師的優秀資源,幫助他們應對日益增長的容錯性、可擴展性和低功耗的需求。它也是教導高級本科生和研究生有關可靠神經形態系統的基本概念、組織和實際硬體-軟體設計的優秀資源,這些系統具備學習和容錯能力。
Abderazek Ben Abdallah is a Full Professor of Computer Science and Engineering, University of Aizu, Aizu-Wakamatus, Japan, since April 2014. He has more than 20- years of experience in research and education of computer systems design and adaptive brain-inspired computing systems. His current research interest lies in studying neural processing systems with a particular focus on spike-based neural network dynamics and spike-based learning. He has authored three books, holds 4 registered and 5 pending Japanese patents, received numerous awards, and published more than 160 journal articles and conference papers.
Khanh N. Dang received his Ph.D. degree from The University of Aizu, Japan in 2017. Since 2017, he has been an assistant professor at VNU Key Laboratory for Smart Integrated Systems, VNU University of Engineering and Technology, Vietnam National University Hanoi (VNU), Hanoi Vietnam. He was a visiting researcher at the University of Aizu in 2019 and 2020-2021. His research interests include neuromorphic computing, 3D Integrated Circuits technology, AI for CAD, and fault-tolerance.
Abderazek Ben Abdallah 自2014年4月起擔任日本會津大學計算機科學與工程的全職教授。他在計算機系統設計和自適應腦啟發計算系統的研究和教育方面擁有超過20年的經驗。他目前的研究興趣在於研究神經處理系統,特別專注於基於脈衝的神經網絡動態和基於脈衝的學習。他已出版三本書籍,擁有4項已註冊和5項待審的日本專利,獲得多項獎項,並發表了超過160篇期刊文章和會議論文。
Khanh N. Dang 於2017年獲得日本會津大學的博士學位。自2017年以來,他一直擔任越南國立大學河內分校(VNU)工程與技術大學VNU智能集成系統重點實驗室的助理教授。他於2019年及2020至2021年期間擔任會津大學的訪問研究員。他的研究興趣包括神經形態計算、3D集成電路技術、用於計算機輔助設計的人工智慧以及容錯技術。