Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms
暫譯: 自我感知安全性在可重構硬體平台中的即時任務排程
Guha, Krishnendu, Saha, Sangeet, Chakrabarti, Amlan
相關主題
商品描述
(a) Reconfigurable hardware based embedded systems
(b) Importance of Real Time Scheduling for such embedded architectures
(c) Importance of Self Aware Security for such architectures
Chapter 2: Background
(a) Scheduling for embedded real time tasks and limitations of existing techniques
(b) Security related to hardware attacks and limitations of existing techniques
Chapter 3: A novel real-time scheduling for FPGAs having slotted area model
This chapter presents deadline-partition oriented scheduling methodologiesfor periodic hard real-time dynamic task sets on fully and partiallyreconfigurable FPGAs in which the floor of the FPGA is assumed to be statically equi-partitioned into a set of homogeneous tiles such that anyarbitrary task of the given task set may be feasibly mapped into the areaof a given tile.
Chapter 4: A novel real-time scheduling for FPGAs having flexible area model
This chapter presents scheduling methodologies for periodic dependent hard real-time dynamic task sets on fully and partially reconfigurable FPGAs in which the floor of the FPGA follows flexible area model such that any task can be placed anywhere within the floor area. This will work will attempt to solve both the temporal and spatial aspects of the scheduling.
Chapter 5: Denial of Service Attacks for Real Time Scheduling and Related Mitigation Techniques
This chapter presents threat analysis associated with denial of service attacks due to delay inducing hardware trojans in embedded architectures for the scheduling strategies presenteed in Chapter 3 and 4. A self aware security module is also presented that detects and mitigates the threat.
Chapter 6: Erroneous Result Generation Attack for Real Time Scheduling and Related Mitigation Technique
This chapter presents threat analysis associated with generation of erroneous results that may jeopardize the real time task schedules presented in Chapter 3 and 4. Related detection and mitigation techniques are presented alongwith. In addition to this, it is also described how related modifications of the self aware security module can ensure security for the present scenario.Chapter 7: Conclusion
In this book, we present the importance of real time scheduling for reconfigurable hardware based embedded platforms and related security needs. We present limitations of existing techniques and present some new real time scheduling techniques suitable for the embedded platform. We also focus on how denial of service and erroneous result generation may take place on the real time schedules due to vulnerability of hardware. Related detection and mitigation techniques are discussed, along with description of a self aware module that facilitates detection and mitigation from such threats.
商品描述(中文翻譯)
第 1 章: 介紹
(a) 可重構硬體基礎的嵌入式系統
(b) 實時排程對於此類嵌入式架構的重要性
(c) 自我感知安全性對於此類架構的重要性
第 2 章: 背景
(a) 嵌入式實時任務的排程及現有技術的限制
(b) 與硬體攻擊相關的安全性及現有技術的限制
第 3 章: 針對具有分槽區域模型的 FPGA 的新型實時排程
本章介紹針對完全和部分可重構 FPGA 上的周期性硬實時動態任務集的截止日期分區導向排程方法論，其中假設 FPGA 的底層靜態均勻劃分為一組同質的瓷磚，以便給定任務集中的任何任務都可以可行地映射到給定瓷磚的區域。
第 4 章: 針對具有靈活區域模型的 FPGA 的新型實時排程
本章介紹針對完全和部分可重構 FPGA 上的周期性依賴硬實時動態任務集的排程方法論，其中 FPGA 的底層遵循靈活區域模型，以便任何任務都可以放置在底層區域的任何位置。這將嘗試解決排程的時間和空間兩個方面。
第 5 章: 實時排程的拒絕服務攻擊及相關緩解技術
本章介紹與由於延遲引起的硬體特洛伊木馬在嵌入式架構中對第 3 章和第 4 章中提出的排程策略造成的拒絕服務攻擊相關的威脅分析。還介紹了一個自我感知安全模組，該模組能夠檢測並緩解這一威脅。
第 6 章: 實時排程的錯誤結果生成攻擊及相關緩解技術
本章介紹與生成可能危害第 3 章和第 4 章中提出的實時任務排程的錯誤結果相關的威脅分析。相關的檢測和緩解技術也一併提出。此外，還描述了自我感知安全模組的相關修改如何確保當前情境的安全性。
第 7 章: 結論
在本書中，我們介紹了實時排程對於可重構硬體基礎嵌入式平台的重要性及相關的安全需求。我們提出了現有技術的限制，並介紹了一些適合嵌入式平台的新實時排程技術。我們還重點討論了由於硬體的脆弱性，拒絕服務和錯誤結果生成如何影響實時排程。相關的檢測和緩解技術也進行了討論，並描述了一個自我感知模組，該模組能夠促進對這些威脅的檢測和緩解。
作者簡介
Dr. Krishnendu Guha is presently an Assistant Professor (On Contract) at National Institute of Technology (NIT), Jamshedpur, India. Prior to this, he was a Visiting Scientist in Indian Statistical Institute (ISI), Kolkata, India from December 2020-February 2021. He was also an Intel India Research Fellow from December 2019- December 2020. He has completed his Ph.D. from University of Calcutta. In his Ph.D. tenure, he received the prestigious INSPIRE Fellowship Award from the Department of Science and Technology, Government of India and the Intel India Final Year Ph.D. Fellowship Award from Intel Corporations, India. He completed his MTech from University of Calcutta, where he was the recipient of the University Gold Medal for securing the First Class First Rank. His present research arena encompasses embedded security, with a flavor of artificial intelligence and nature-inspired strategies.
Dr. Sangeet Saha received his Ph.D. degree in Information Technology from the University of Calcutta, India in 2018. He received the TCS Industry Fellowship Award during his Ph.D. After submitting his Ph.D. thesis in 2017, he worked as a visiting scientist at Indian Statistical Institute (ISI) Kolkata, India. Since May 1, 2018 he is a Senior Research Officer in EPSRC National Centre for Nuclear Robotics, based in the EIS Lab, School of Computer Science and Electronic Engineering at University of Essex, UK. Primarily, his research expertise is in embedded systems, with specific interests that include real-time scheduling, scheduling for reconfigurable computers, fault-tolerance, and approximation-based real-time computing.
Prof. (Dr.) Amlan Chakrabarti is presently Professor and Director of A. K. Choudhury School of Information Technology (AKCSIT), University of Calcutta. Prior to this, he completed his post-doctoral research at Princeton University after completing his Ph.D. from the University of Calcutta in association with ISI, Kolkata. He has been associated with research projects funded by government agencies and industries related to Reconfigurable Architecture, VLSI Design, Security for Cyber-physical Systems, Internet of Things, Machine Learning, Computer Vision and Quantum Computing. He is the Series Editor of Springer Transactions on Computer Systems and Networks and Associate Editor of Elsevier Journal of Computers and Electrical Engineering. His present research interests include Reconfigurable Computing, Embedded Systems Design, VLSI Design, Quantum Computing and Computer Vision. He is a Distinguished Visitor of IEEE Computer Society and Distinguished Speaker of ACM (2017-2020).
作者簡介(中文翻譯)
克里什嫩杜·古哈博士目前是印度賈姆謝德布爾國立技術學院（NIT）的合約助理教授。在此之前，他於2020年12月至2021年2月擔任印度統計學院（ISI）科爾卡塔的訪問科學家。他還曾於2019年12月至2020年12月擔任英特爾印度研究獎學金獲得者。他在加爾各答大學完成了博士學位。在博士期間，他獲得了印度政府科學與技術部頒發的INSPIRE獎學金以及英特爾公司頒發的印度最終年博士獎學金。他在加爾各答大學完成了碩士學位，並因獲得一級第一名而獲得大學金獎。他目前的研究領域包括嵌入式安全，並結合人工智慧和自然啟發策略。
桑吉特·薩哈博士於2018年在印度加爾各答大學獲得資訊技術博士學位。在博士期間，他獲得了TCS產業獎學金。2017年提交博士論文後，他在印度統計學院（ISI）科爾卡塔擔任訪問科學家。自2018年5月1日起，他在英國埃塞克斯大學計算機科學與電子工程學院的EPSRC國家核機器人中心擔任高級研究官。他的研究專長主要在嵌入式系統，具體興趣包括實時排程、可重構計算機的排程、容錯和基於近似的實時計算。
阿姆蘭·查克拉巴提教授（博士）目前是加爾各答大學A.K.喬杜里資訊技術學院（AKCSIT）的教授及主任。在此之前，他在普林斯頓大學完成博士後研究，並在加爾各答大學與ISI合作完成博士學位。他參與了由政府機構和產業資助的研究項目，涉及可重構架構、VLSI設計、網路物理系統的安全性、物聯網、機器學習、計算機視覺和量子計算。他是Springer《計算機系統與網路交易》系列的編輯，以及Elsevier《計算機與電氣工程期刊》的副編輯。他目前的研究興趣包括可重構計算、嵌入式系統設計、VLSI設計、量子計算和計算機視覺。他是IEEE計算機學會的傑出訪客及ACM的傑出演講者（2017-2020）。
