Principles of Secure Processor Architecture Design
暫譯: 安全處理器架構設計原則

Szefer, Jakub, Martonosi, Margaret

  • 出版商: Morgan & Claypool
  • 出版日期: 2018-10-18
  • 售價: $3,210
  • 貴賓價: 9.5$3,050
  • 語言: 英文
  • 頁數: 173
  • 裝訂: Hardcover - also called cloth, retail trade, or trade
  • ISBN: 1681734044
  • ISBN-13: 9781681734040
  • 海外代購書籍(需單獨結帳)

商品描述

With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered).

This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.

商品描述(中文翻譯)

隨著對計算機安全以及在商用計算機上執行的代碼和數據保護的興趣日益增長,當今處理器中的硬體安全功能在近幾年顯著增加。這些安全功能不再僅僅是學術上的興趣,業界也已經接受了處理器內部的安全功能,目前市場上有多種商用安全處理器架構可供選擇。本書旨在讓讀者了解學術和商用安全處理器架構設計背後的原則。安全處理器架構研究專注於探索和設計計算機處理器內部的硬體功能,這些功能可以幫助保護在處理器上執行的代碼和數據的機密性和完整性。與傳統的處理器架構研究專注於性能、效率和能耗作為首要設計目標不同,安全處理器架構設計將安全性作為首要設計目標(同時仍然將其他方面視為需要考慮的重要設計因素)。

本書旨在向對架構和硬體安全研究感興趣的研究生以及希望在其設計中添加安全功能的業界計算機架構師介紹安全處理器架構設計的不同挑戰。它旨在教育讀者如何解決過去的不同挑戰以及最佳實踐,即設計新安全處理器架構的原則。基於對許多計算機架構師和安全研究者過去工作的仔細回顧,讀者還將了解安全處理器架構設計所需的五個基本原則。本書還介紹了現有的研究挑戰和潛在的新研究方向。最後,本書提供了許多設計建議,並討論了設計師應避免的陷阱和謬誤。