Multi-Core Cache Hierarchies (Paperback)
暫譯: 多核心快取層級 (平裝本)

Rajeev Balasubramonian, Norman Jouppi

  • 出版商: Morgan & Claypool
  • 出版日期: 2011-05-23
  • 售價: $1,780
  • 貴賓價: 9.5$1,691
  • 語言: 英文
  • 頁數: 154
  • 裝訂: Paperback
  • ISBN: 1598297538
  • ISBN-13: 9781598297539
  • 海外代購書籍(需單獨結帳)

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商品描述

A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints.

The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research.

The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers.

Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks

商品描述(中文翻譯)

整體系統性能和功耗的關鍵決定因素是快取層級,因為訪問外部記憶體所消耗的週期和能量遠高於內部快取的訪問。此外,多核心處理器預期對記憶體系統提出更高的頻寬需求。所有這些問題使得透過提高內部快取的效率來避免外部記憶體訪問變得重要。未來的多核心處理器將擁有許多大型快取銀行,這些快取銀行通過網路連接並由多個核心共享。因此,必須解決許多重要問題:快取資源必須在多個核心之間分配,數據必須放置在接近訪問核心的快取銀行中,並且必須識別出最重要的數據以進行保留。最後,現有技術在擴展方面的困難要求我們適應並利用新的技術限制。

本書試圖綜合近期針對多核心處理器的快取研究創新。這是希望了解近期快取研究現狀的早期研究生、研究人員和實務工作者的絕佳起點。

本書適合作為高級計算機架構課程的參考資料,也適合經驗豐富的研究人員和VLSI工程師。

目錄:大型快取設計的基本元素 / CMP 最後級快取中的數據組織 / 影響快取命中率的政策 / 大型快取內的互連網路 / 技術 / 總結性評論

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