Robust SRAM Designs and Analysis (Hardcover)
暫譯: 穩健的SRAM設計與分析（精裝版）

Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan

Robust SRAM Designs and Analysis (Hardcover)

買這商品的人也買了...

相關主題

商品描述

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.

  • Provides a complete and concise introduction to SRAM bitcell design and analysis;
  • Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
  • Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
  • Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

商品描述(中文翻譯)

本書提供靜態隨機存取記憶體（Static Random Access Memory, SRAM）位元單元設計與分析的指南，以應對CMOS裝置及新興裝置（如隧道場效應電晶體，Tunnel FETs）在奈米範疇中的挑戰。由於製程變異在大型記憶體陣列中持續存在，本書強調了最受歡迎的SRAM位元單元拓撲（基準電路），這些拓撲能夠減輕變異的影響，並提供詳盡的分析。書中還包含實驗模擬設置，涵蓋了SRAM設計與分析中的奈米範疇挑戰，如製程變異、漏電流和NBTI。全書強調了實現最佳SRAM位元單元設計的各種權衡。

- 提供SRAM位元單元設計與分析的完整且簡明的介紹；
- 提供應對奈米範疇挑戰（如製程變異、漏電流和NBTI）的方法；
- 包含提取CMOS技術和新興裝置不同設計指標的模擬設置；
- 強調實現最佳SRAM位元單元設計的不同權衡。

類似商品