Computer Arithmetic and Verilog HDL Fundamentals (Hardcover)

Joseph Cavanagh

Computer Arithmetic and Verilog HDL Fundamentals (Hardcover)
  • 出版商: CRC
  • 出版日期: 2009-11-01
  • 售價: $7,760
  • 貴賓價: 9.5 折 $7,372
  • 語言: 英文
  • 頁數: 971
  • 裝訂: Hardcover
  • ISBN: 1439811245
  • ISBN-13: 9781439811245
  • 相關分類: Verilog

    • 海外代購書籍(需單獨結帳)

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商品描述

Verilog Hardware Description Language (HDL) is the state-of-the-art method for designing digital and computer systems. Ideally suited to describe both combinational and clocked sequential arithmetic circuits, Verilog facilitates a clear relationship between the language syntax and the physical hardware. It provides a very easy-to-learn and practical means to model a digital system at many levels of abstraction.

Computer Arithmetic and Verilog HDL Fundamentals details the steps needed to master computer arithmetic for fixed-point, decimal, and floating-point number representations for all primary operations. Silvaco International’s SILOS, the Verilog simulator used in these pages, is simple to understand, yet powerful enough for any application. It encourages users to quickly prototype and de-bug any logic function and enables single-stepping through the Verilog source code. It also presents drag-and-drop abilities.

Introducing the three main modeling methods—dataflow, behavioral, and structural—this self-contained tutorial—

  • Covers the number systems of different radices, such as octal, decimal, hexadecimal, and binary-coded variations

  • Reviews logic design fundamentals, including Boolean algebra and minimization techniques for switching functions

  • Presents basic methods for fixed-point addition, subtraction, multiplication, and division, including the use of decimals in all four operations

  • Addresses floating-point addition and subtraction with several numerical examples and flowcharts that graphically illustrate steps required for true addition and subtraction for floating-point operands

  • Demonstrates floating-point division, including the generation of a zero-biased exponent

Designed for electrical and computer engineers and computer scientists, this book leaves nothing unfinished, carrying design examples through to completion. The goal is practical proficiency. To this end, each chapter includes problems of varying complexity to be designed by the reader.

商品描述(中文翻譯)

Verilog 硬體描述語言（HDL）是設計數位和電腦系統的最先進方法。Verilog 非常適合描述組合和時序算術電路，能夠清晰地將語言語法與實際硬體之間建立關聯。它提供了一種非常易於學習和實用的方式，可以在多個抽象層次上對數位系統進行建模。

《計算機算術和 Verilog HDL 基礎》詳細介紹了掌握固定點、十進制和浮點數表示法的計算機算術所需的步驟，包括所有主要操作。這本書使用的 Verilog 模擬器 SILOS 是 Silvaco International 公司開發的，它簡單易懂，但功能強大，適用於任何應用。它鼓勵用戶快速原型製作和調試任何邏輯功能，並能夠逐步執行 Verilog 源代碼。它還提供了拖放功能。

本書介紹了三種主要的建模方法：數據流、行為和結構。這本自包含的教程：

- 詳細介紹了不同進制的數字系統，如八進制、十進制、十六進制和二進制編碼變體。
- 回顧了邏輯設計的基礎知識，包括布爾代數和用於開關函數的最小化技術。
- 提供了固定點加法、減法、乘法和除法的基本方法，包括在這四種操作中使用小數的方法。
- 詳細介紹了浮點數加法和減法，並提供了幾個數值示例和流程圖，以圖形方式說明浮點數操作數進行真正的加法和減法所需的步驟。
- 演示了浮點數除法，包括生成零偏指數的方法。

本書針對電氣工程師、計算機工程師和計算機科學家設計，不遺餘力地完成了所有內容，並通過設計示例將讀者引導至實際應用。目標是實用的熟練度。為此，每章都包含了各種複雜程度的問題，供讀者設計解決。

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