Verilog HDL Design Examples

Joseph Cavanagh

  • 出版商: CRC
  • 出版日期: 2017-10-13
  • 售價: $7,230
  • 貴賓價: 9.5$6,869
  • 語言: 英文
  • 頁數: 673
  • 裝訂: Hardcover
  • ISBN: 1138099953
  • ISBN-13: 9781138099951
  • 相關分類: Verilog
  • 海外代購書籍(需單獨結帳)

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商品描述

The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles―including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).

商品描述(中文翻譯)

Verilog 語言提供了一種手段,可以在多個抽象層次上對數位系統進行建模,從邏輯閘到複雜的數位系統,再到大型電腦。本書的目的是介紹 Verilog 語言,並提供各種範例,以便讀者能夠在使用 Verilog HDL 設計數位系統方面打下堅實的基礎。Verilog 專案包括設計模組、測試平台模組,以及從模擬器獲得的輸出,這些輸出展示了設計的完整功能運作。在適用的情況下,將詳細回顧主題的理論,並介紹邏輯設計原則,包括:狀態圖、卡諾圖、方程式和邏輯圖。書中包含了大量的範例和作業問題。這些範例包括邏輯運算、不同模數的計數器、半加器、全加器、進位預測加法器、陣列乘法器、不同類型的 Moore 和 Mealy 機器,以及算術邏輯單元 (ALUs)。