Nanoelectronics: Materials to Chips Design
暫譯: 奈米電子學：材料到晶片設計

這本書以獨特的方式解釋奈米材料和裝置，並分析其設計參數，以應對低功耗晶片設計中的亞奈米範疇挑戰。由於製程變異、裝置尺寸和電源縮放在超大規模集成（VLSI）電路設計中仍然是持續的挑戰，本書強調了傳統和新穎的奈米材料、裝置和電路、漏電流減少技術以及其他重要的權衡，並進行了詳盡的分析。本書在高效能和低功耗VLSI裝置及電路的共同設計上，特別強調了各種權衡。

本書內容包括：

- 討論先進的奈米半導體裝置，如FinFET、奈米線、隧道場效應電晶體、碳納米管場效應電晶體和高電子遷移率電晶體。
- 提出在奈米技術節點下的高效能半導體裝置，以分析量子效應及其對電路和系統的影響。
- 涵蓋高效能裝置的功率耗散和減少技術。
- 解釋矽和非矽裝置在數位邏輯及類比/射頻應用中的各種應用。
- 檢視極低功耗類比集成電路的困難和實際設計方法。

本書主要為電機工程、電子與通訊工程、材料科學、奈米科學及奈米技術領域的高年級本科生、研究生和學術研究人員所撰寫。

Balwinder Raj (MIEEE'2006) is currently working as Associate Professor at the National Institute of Technology Jalandhar, India. He has more than 15 years of teaching and research experience. He did BTech in Electronics Engineering (PTU Jalandhar), MTech in Microelectronics (PU Chandigarh), and PhD in VLSI Design (IIT Roorkee), India, in 2004, 2006, and 2010, respectively. For further research work, the European Commission awarded him the "Erasmus Mundus" Mobility of Life research fellowship for postdoc research work at the University of Rome, Tor Vergata, Italy, in 2010-2011. Dr Raj received India4EU (India for European Commission) Fellowship and worked as visiting researcher at KTH University, Stockholm, Sweden, October-November 2013. He also visited Aalto University in Finland as visiting researcher during June 2017.

He had received Best Teacher Award from the Indian Society for Technical Education (ISTE), New Delhi, in 26 July 2013. Dr Raj received the Young Scientist Award from the Punjab Academy of Sciences during 18th Punjab Science Congress held on 9 February 2015. He has also received research paper award in the International Conference on Electrical and Electronics Engineering held at Pattaya, Thailand, from 11 to 12 July 2015. Dr Raj has authored/co-authored 8 books, 15 book chapters, and more than 150 research papers in peer-reviewed international/national journals and conferences. His areas of interest in research are classical/non-classical nanoscale semiconductor device modeling; nanoelectronics and their applications in hardware security; sensors and circuit design; FinFET-based memory design; low-power VLSI design; digital/analog VLSI design; and FPGA implementation.

Suman Lata Tripathi is working as Professor in Lovely Professional University with more than 21 years of experience in academics and research. She has completed her PhD in the area of microelectronics and VLSI design from MNNIT, Allahabad, India. She did her MTech in Electronics Engineering from UP Technical University, Lucknow, and BTech in Electrical Engineering from Purvanchal University, Jaunpur, India. She is also a remote post-doc researcher at Nottingham Trent University, London, UK, in the year 2022. She has published more than 102 research papers in refereed Springer, Elsevier, IEEE, and IOP science journals; conference proceeding; and e-books. She has also published 13 Indian patents and 4 copyrights. She has guided four PhD scholars and four are under submission stage. She has organized several workshops, summer internships, and expert lectures for students. She has worked as a session chair, conference steering committee member, editorial board member, and peer reviewer in international/national IEEE, Springer, Wiley, etc., journal and conferences. She has received the "Research Excellence Award" in 2019 and "Research Appreciation Award" in 2020 and 2021 at Lovely Professional University, India. She is recipient of IGEN Women's for Green Technology "Women's Achievers Award" on International Women's Day, 8 March 2023. She had received the best paper at IEEE ICICS-2018. She has also received funded project from SERB DST under the scheme TARE in the area of microelectronic devices. She has edited and authored more than 19 books in different areas of Electronics and Electrical Engineering. She is associated for editing work with top publishers like Elsevier, CRC Taylor and Francis, Wiley-IEEE, SP Wiley, Nova Science, and Apple Academic Press. She is also working as book series editor for title, "Smart Engineering Systems" CRC Press, "Engineering System Design for Sustainable Developments", and "Decentralized Systems & Next Generation Internet" Wiley-Scrivener, and conference series editor for "Conference Proceedings Series on Intelligent Systems for Engineering Designs" CRC Press Taylor & Francis. She is serving as academic editor of Journal of Electrical and Computer Engineering (Scopus/WoS, Q2), International Journal of Reconfigurable Computing (Scopus, Q3), and Active and Passive Electronic Component (Scopus, Q4), Hindawi. She is associated as senior member IEEE, Fellow IETE, and Life member ISC and is continuously involved in different professional activities along with academic work. Her area of expertise includes microelectronics device modeling and characterization, low-power VLSI circuit design, VLSI design of testing, and advanced FET design for IoT, embedded system design, reconfigurable architecture with FPGAs, and biomedical applications.

Tarun Chaudhary did her BTech in Electronics and Communication Engineering from UIET, Panjab University, Chandigarh, in 2010; MTech. in VDAT (ECE) from NIT Hamirpur, Himachal Pradesh, in 2012; and PhD from NIT Hamirpur, Himanchal Pradesh, India, in the year 2017. During her PhD she has worked on the designing and mathematical modeling of vertical FET. She is currently working as Assistant Professor in ECE Department, Dr B R Ambedkar National Institute of Technology Jalandhar, India. She has worked as a faculty member under SMDP C2SD Project from October 2017 till November 2019. She is guiding PhD and PG scholars in the areas of nanoscale devices and circuits, and FPGAbased design. She has 5 book chapters and more than 25 research papers in peer-reviewed international/national journals and conferences. She has organized several STCs and workshops in the domain of VLSI design. Of the three students who are pursuing their PhD under her supervision, all are working on TFETs, NCFETs, and nanowire-based sensors. Her present research is largely focused on the design and modeling of nanoscale devices, TFETs, junctionless devices, and low-power VLSI design circuits.

Mandeep Singh has done his BTech in Electronics and Communication Engineering, MTech ECE (VLSI DESIGN) from Punjabi University, Patiala, and PhD from NIT Jalandhar, Punjab, India. He has eight-year teaching experience to teach undergraduate and master students in Punjab Technical University, India; the National Institute of Technology Uttarakhand, India; and Chaudhary Charan Singh University, Meerut, UP, India. Currently he is working as Postdoc Researcher in the Indian Institute of Technology Kanpur, UP, India. He has published various research papers in the domain of VLSI design and circuit. His areas of research are semiconductor device modeling, memory designs, CNT and nanowires, and low-power VLSI designs.

Balwinder Raj（MIEEE'2006）目前擔任印度賈蘭達爾國立技術學院的副教授。他擁有超過15年的教學和研究經驗。他於2004年、2006年和2010年分別在印度賈蘭達爾的PTU獲得電子工程學士學位、在昌迪加爾的PU獲得微電子碩士學位，以及在印度魯爾基的IIT獲得VLSI設計博士學位。為了進一步的研究工作，歐洲委員會於2010-2011年授予他「Erasmus Mundus」流動生活研究獎學金，以進行在意大利羅馬托爾維爾加大學的博士後研究。Raj博士於2013年10月至11月獲得India4EU（印度為歐洲委員會）獎學金，並在瑞典斯德哥爾摩的KTH大學擔任訪問研究員。他於2017年6月作為訪問研究員造訪芬蘭的阿爾托大學。

他於2013年7月26日獲得印度技術教育學會（ISTE）頒發的最佳教師獎。Raj博士於2015年2月9日的第18屆旁遮普科學大會上獲得旁遮普科學院的青年科學家獎。他還在2015年7月11日至12日於泰國芭堤雅舉行的國際電氣與電子工程會議上獲得研究論文獎。Raj博士已撰寫或共同撰寫8本書籍、15個書章，以及在同行評審的國際/國內期刊和會議上發表超過150篇研究論文。他的研究興趣包括經典/非經典納米尺度半導體器件建模；納米電子學及其在硬體安全中的應用；傳感器和電路設計；基於FinFET的記憶體設計；低功耗VLSI設計；數位/類比VLSI設計；以及FPGA實現。

Suman Lata Tripathi在Lovely Professional University擔任教授，擁有超過21年的學術和研究經驗。她在印度阿拉哈巴德的MNNIT完成了微電子學和VLSI設計的博士學位。她在印度勒克瑙的UP技術大學獲得電子工程碩士學位，並在印度賈雲普的Purvanchal大學獲得電氣工程學士學位。她還於2022年在英國倫敦的諾丁漢特倫特大學擔任遠程博士後研究員。她已在Springer、Elsevier、IEEE和IOP科學期刊上發表超過102篇研究論文；會議論文集；和電子書。她還獲得了13項印度專利和4項版權。她指導了四名博士生，另有四名正在提交階段。她為學生組織了多個工作坊、暑期實習和專家講座。她曾擔任國際/國內IEEE、Springer、Wiley等期刊和會議的會議主席、會議指導委員會成員、編輯委員會成員和同行評審。她在Lovely Professional University於2019年獲得「研究卓越獎」，並在2020年和2021年獲得「研究表彰獎」。她於2023年3月8日國際婦女節獲得IGEN女性綠色科技「女性成就獎」。她在IEEE ICICS-2018上獲得最佳論文獎。她還獲得了來自SERB DST的資助項目，該項目在微電子器件領域的TARE計劃下進行。她編輯和撰寫了超過19本電子和電氣工程不同領域的書籍。她與Elsevier、CRC Taylor and Francis、Wiley-IEEE、SP Wiley、Nova Science和Apple Academic Press等頂級出版商合作進行編輯工作。她還擔任CRC Press的「智慧工程系統」書系列、Wiley-Scrivener的「可持續發展的工程系統設計」和「去中心化系統與下一代互聯網」的書系列編輯，以及CRC Press Taylor & Francis的「智能系統工程設計會議論文集系列」的會議系列編輯。她擔任《電氣與計算機工程期刊》（Scopus/WoS, Q2）、《可重構計算國際期刊》（Scopus, Q3）和《主動與被動電子元件》（Scopus, Q4）Hindawi的學術編輯。她是IEEE的高級會員、IETE的院士，以及ISC的終身會員，並持續參與各種專業活動及學術工作。她的專業領域包括微電子器件建模與特性分析、低功耗VLSI電路設計、VLSI測試設計，以及針對物聯網的先進FET設計、嵌入式系統設計、基於FPGA的可重構架構和生物醫學應用。

Tarun Chaudhary於2010年在印度昌迪加爾的Panjab University UIET獲得電子與通信工程學士學位；2012年在喜馬偕爾邦的NIT Hamirpur獲得VDAT（ECE）碩士學位；並於2017年在NIT Hamirpur獲得博士學位。在她的博士研究期間，她專注於垂直FET的設計和數學建模。她目前在印度賈蘭達爾的Dr B R Ambedkar國立技術學院的ECE系擔任助理教授。她在2017年10月至2019年11月期間，作為SMDP C2SD項目的教職員工。她指導博士和碩士研究生，研究領域包括納米尺度器件和電路，以及基於FPGA的設計。她擁有5個書章和超過25篇在同行評審的國際/國內期刊和會議上發表的研究論文。她在VLSI設計領域組織了多個STC和工作坊。在她指導的三名博士生中，所有人都在研究TFET、NCFET和基於納米線的傳感器。她目前的研究主要集中在納米尺度器件的設計和建模、TFET、無接面器件和低功耗VLSI設計電路。

Mandeep Singh獲得電子與通信工程學士學位，並在印度帕提亞拉的旁遮普大學獲得電子與通信工程（VLSI設計）碩士學位，之後在印度賈蘭達爾的NIT獲得博士學位。他在印度旁遮普技術大學、印度烏塔拉坎德國立技術學院和印度梅魯特的查烏達里查蘭辛大學擔任本科生和碩士生的教學工作，擁有八年的教學經驗。目前，他在印度烏普的印度理工學院坎普爾擔任博士後研究員。他在VLSI設計和電路領域發表了多篇研究論文。他的研究領域包括半導體器件建模、記憶體設計、CNT和納米線，以及低功耗VLSI設計。