Performance Modeling For Computer Architects

Krishna

Performance Modeling For Computer Architects
  • 出版商: Wiley
  • 出版日期: 1995-10-14
  • 售價: $3,630
  • 貴賓價: 9.5 折 $3,449
  • 語言: 英文
  • 頁數: 408
  • 裝訂: Paperback
  • ISBN: 0818670940
  • ISBN-13: 9780818670947

    • 海外代購書籍(需單獨結帳)

買這商品的人也買了...

相關主題

商品描述

Description:

As computers become more complex, the number and complexity of the tasks facing the computer architect have increased. Computer performance often depends in complex way on the design parameters and intuition that must be supplemented by performance studies to enhance design productivity.

This book introduces computer architects to computer system performance models and shows how they are relatively simple, inexpensive to implement, and sufficiently accurate for most purposes. It discusses the development of performance models based on queuing theory and probability. The text also shows how they are used to provide quick approximate calculations to indicate basic performance tradeoffs and narrow the range of parameters to consider when determining system configurations. It illustrates how performance models can demonstrate how a memory system is to be configured, what the cache structure should be, and what incremental changes in cache size can have on the miss rate. A particularly deep knowledge of probability theory or any other mathematical field to understand the papers in this volume is not required.

 

Table of Contents:

Preface.

Computer Performance Evaluation Methodology.

An Instruction Timing Model of CPU Performance.

On Parallel Processing Systems: Amdahl's Law Generalized and Some Results on Optimal Design.

The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.

Classification and Performance Evaluation of Instruction Buffering Techniques.

Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance.

Optimal Pipelining.

Branch Strategies: Modeling and Optimization.

Footprints in the Cache.

An Analytical Cache Model.

Modeling Live and Dead Lines in Cache Memory Systems.

Optimal Partitioning of Cache Memory.

An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols.

Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling.

Analysis of Multiprocessors with Private Cache Memories.

Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme.

Performance of Processor-Memory Interconnections for Multiprocessors.

General Model for Memory Interference in Multiprocessors and Mean Value Analysis.

Equilibrium Point Analysis of Memory Interference in Multiprocessor Systems.

Scalar Memory References in Pipelined Multiprocessors: A Performance Study.

Performance Measurement and Modeling to Evaluate Various Effects on a Shared Memory Multiprocessor.

Optimal Design of Multilevel Storage Hierarchies.

Analysis of the Periodic Update Write Policy for Disk Cache.

Models of DASD Subsystems with Multiple Access Paths: A Throughput-Driven Approach.

Synchronized Disk Interleaving.

Asynchronous Disk Interleaving: Approximating Access Delays.

An Analytic Performance Model of Disk Arrays.

About the Author.

商品描述(中文翻譯)

描述：
隨著電腦變得越來越複雜，電腦架構師面臨的任務數量和複雜性也隨之增加。電腦性能往往以複雜的方式依賴於設計參數和直覺，這些都必須通過性能研究來補充，以提高設計生產力。本書向電腦架構師介紹電腦系統性能模型，並展示這些模型相對簡單、實施成本低且對於大多數目的來說足夠準確。它討論了基於排隊理論和概率的性能模型的發展。文本還展示了如何使用這些模型來提供快速的近似計算，以指示基本的性能權衡，並縮小在確定系統配置時需要考慮的參數範圍。它說明了性能模型如何展示記憶體系統的配置方式、快取結構應該是什麼，以及快取大小的增量變化對未命中率的影響。理解本卷中的論文不需要對概率論或其他數學領域有特別深入的知識。

目錄：
前言。
電腦性能評估方法論。
CPU性能的指令計時模型。
關於平行處理系統：阿姆達爾法則的推廣及最佳設計的一些結果。
指令級和機器平行性的非均勻分佈及其對性能的影響。
指令緩衝技術的分類與性能評估。
評估管線性能的程序中的分支和數據依賴性特徵。
最佳管線化。
分支策略：建模與優化。
快取中的足跡。
一個分析性快取模型。
在快取記憶體系統中建模活線和死線。
快取記憶體的最佳劃分。
一種準確且高效的性能分析技術，用於多處理器監視快取一致性協議。
通過數據引用建模分析多處理器快取行為。
分析具有私有快取記憶體的多處理器。
使用偏斜存儲方案的平行記憶體中的向量訪問性能。
多處理器的處理器-記憶體互連性能。
多處理器中記憶體干擾的一般模型及均值分析。
多處理器系統中記憶體干擾的平衡點分析。
在管線多處理器中的標量記憶體引用：性能研究。

類似商品