Modern Receiver Front-Ends: Systems, Circuits, and Integration
Joy Laskar, Babak Matinpour, Sudipto Chakraborty
- 出版商: Wiley
- 出版日期: 2004-02-13
- 售價: $5,790
- 貴賓價: 9.5 折 $5,501
- 語言: 英文
- 頁數: 240
- 裝訂: Hardcover
- ISBN: 0471225916
- ISBN-13: 9780471225911
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商品描述
Description:
Architectures BABAK MATINPOUR and JOY LASKAR
* Describes the actual implementation of receiver architectures from the initial design to an IC-based product
* Presents many tricks-of-the-trade not usually covered in textbooks
* Covers a range of practical issues including semiconductor technology selection, cost versus performance, yield, packaging, prototype development, testing, and analysis
* Discusses architectures that are employed in modern broadband wireless systems
Table of Contents:
Preface.
Acknowledgments.
1 INTRODUCTION.
1.1 Current State of the Art.
2 RECEIVER SYSTEM DESIGN.
2.1 Frequency Planning.
2.1.1 Blockers.
2.1.2 Spurs and Desensing.
2.1.3 Transmitter Leakage.
2.1.4 LO Leakage and Interference.
2.1.5 Image.
2.1.6 Half IF.
2.2 Link Budget Analysis.
2.2.1 Linearity.
2.2.2 Noise.
2.2.3 Signal-to-Noise Ratio.
2.2.4 Receiver Gain.
2.3 Propagation Effects.
2.3.1 Path Loss.
2.3.2 Multipath and Fading.
2.3.3 Equalization.
2.3.4 Diversity.
2.3.5 Coding.
2.4 Interface Planning.
2.5 Conclusion.
3 REVIEW OF RECEIVER ARCHITECTURES.
3.1 Heterodyne Receivers.
3.2 Image Reject Receivers.
3.2.1 Hartley Architecture.
3.2.2 Weaver Architecture.
3.3 Zero IF Receivers.
3.4 Low IF Receivers.
3.5 I ssues in Direct Conversion Receivers.
3.5.1 Noise.
3.5.2 LO Leakage and Radiation.
3.5.3 Phase and Amplitude Imbalance.
3.5.4 DC Offset.
3.5.5 Intermodulations.
3.6 Architecture Comparison and Trade-off.
3.7 Conclusion.
4 SILICON-BASED RECEIVER DESIGN.
4.1 Receiver Architecture and Design.
4.1.1 System Description and Calculations.
4.1.2 Basics of OFDM.
4.1.3 System Architectures.
4.1.4 System Calculations.
4.2 Circuit Design.
4.2.1 SiGe BiCMOS Process Technology.
4.2.2 LNA.
4.2.3 Mixer.
4.2.4 Frequency Divider.
4.3 Receiver Design Steps.
4.3.1 Design and Integration of Building Blocks.
4.3.2 DC Conditions.
4.3.3 Scattering Parameters.
4.3.4 Small-Signal Performance.
4.3.5 Transient Performance.
4.3.6 Noise Performance.
4.3.7 Linearity Performance.
4.3.8 Parasitic Effects.
4.3.9 Process Variation.
4.3.10 50-Ω and Non-50-Ω Receivers.
4.4 Layout Considerations.
4.5 Characterization of Receiver Front-Ends.
4.5.1 DC Test.
4.5.2 Functionality Test.
4.5.3 S-Parameter Test.
4.5.4 Conversion Gain Test.
4.5.5 Linearity Test.
4.5.6 Noise Figure Test.
4.5.7 I/Q Imbalance.
4.5.8 DC Offset.
4.6 Measurement Results and Discussions.
4.6.1 Close Examination of Noise Figure and I/Q Imbalance.
4.6.2 Comments on I/Q Imbalance.
4.7 Conclusion.
5 SUBHARMONIC RECEIVER DESIGNS.
5.1 Illustration of Subharmonic Techniques.
5.2 Mixing Using Antisymmetric I–V Characteristics.
5.3 Impact of Mismatch Effects.
5.4 DC Offset Cancellation Mechanisms.
5.4.1 Intrinsic DC Offset Cancellation.
5.4.2 Extrinsic DC Offset Cancellation.
5.5 Experimental Verification of DC Offset.
5.6 Waveform Shaping Before Mixing.
5.6.1 Theory and Analysis.
5.6.2 Experimental Verification on GaAs MESFET APDP.
5.6.3 Implementation in Silicon.
5.7 Design Steps for APDP-Based Receivers.
5.8 Architectural Illustration.
5.9 Fully Monolithic Receiver Design Using Passive APDP Cores.
5.9.1 Integrated Direct Conversion Receiver MMIC’s.
5.9.2 Receiver Blocks.
5.9.3 Additional Receiver Blocks.
5.10 Reconfigurable Multiband Subharmonic Front-Ends.
5.11 Conclusion.
6 ACTIVE SUBHARMONIC RECEIVER DESIGNS.
6.1 Stacking of Switching Cores.
6.1.1 Description and Principles.
6.1.2 Subharmonic Receiver Architecture.
6.2 Parallel Transistor Stacks.
6.2.1 Active Mixer.
6.2.2 Receiver Architecture.
6.2.3 Extension to Passive Mixers.
6.3 Extension to Higher-Order LO Subharmonics.
6.4 Multiple Phase Signal Generation from Oscillators.
6.5 Future Direction and Conclusion.
7 DESIGN AND INTEGRATION OF PASSIVE COMPONENTS.
7.1 System on Package (SoP).
7.1.1 Multilayer Bandpass Filter.
7.1.2 Multilayer Balun Structure.
7.1.3 Module-Integrable Antennaw.
7.1.4 Fully Integrated SoP Module.
7.2 On-Chip Inductors.
7.2.1 Inductor Modeling.
7.2.2 Inductor Parameters.
7.2.3 Application in Circuits.
7.3 Capacitors.
7.4 Differentially Driven Inductors.
7.5 Transformers.
7.5.1 Electrical Parameters.
7.5.2 Physical Construction.
7.5.3 Electrical Models.
7.5.4 Frequency Response of Transformers.
7.5.5 Step-Up/Step-Down Transformers and Circuit Applications.
7.6 On-Chip Filters.
7.6.1 Filters Using Bond Wires.
7.6.2 Active Filters.
7.7 On-Wafer Antennas.
7.8 Wafer-Level Packaging.
7.9 Conclusion.
8 DESIGN FOR INTEGRATION.
8.1 System Design Considerations.
8.1.1 I/O Counts.
8.1.2 Cross-Talk.
8.1.3 Digital Circuitry Noise.
8.2 IC Floor Plan.
8.2.1 Signal Flow and Substrate Coupling.
8.2.2 Grounding.
8.2.3 Isolation.
8.3 Packaging Considerations.
8.3.1 Package Modeling.
8.3.2 Bonding Limitation.
8.4 Conclusion.
9 FUTURE TRENDS.
9.1 CMOS Cellphones.
9.2 Multiband, Multimode Wireless Solutions.
9.3 60 GHz Subsystems in Silicon!
9.4 Interchip Communications.
9.5 Ultrawideband Communication Technology.
9.6 Diversity Techniques.
9.7 Conclusion.
Index.
商品描述(中文翻譯)
描述：
建築師BABAK MATINPOUR和JOY LASKAR
*描述了從初始設計到基於IC的產品的實際接收器架構實現
*介紹了許多通常不在教科書中涵蓋的實用技巧
*涵蓋了一系列實際問題，包括半導體技術選擇、成本與性能、產量、封裝、原型開發、測試和分析
*討論了在現代寬頻無線系統中使用的架構
目錄：
前言。
致謝。
1 簡介。
1.1 目前的技術水平。
2 接收器系統設計。
2.1 頻率規劃。
2.1.1 阻塞器。
2.1.2 雜訊和抑制。
2.1.3 發射機洩漏。
2.1.4 LO洩漏和干擾。
2.1.5 影像。
2.1.6 半IF。
2.2 連結預算分析。
2.2.1 線性度。
2.2.2 雜訊。
2.2.3 信噪比。
2.2.4 接收增益。
2.3 傳播效應。
2.3.1 路徑損耗。
2.3.2 多徑和衰落。
2.3.3 均衡。
2.3.4 多樣性。
2.3.5 編碼。
2.4 介面規劃。
2.5 結論。
3 接收器架構回顧。
3.1 雜頻接收器。
3.2 抑制影像接收器。
3.2.1 Hartley架構。
3.2.2 Weaver架構。
3.3 零IF接收器。
3.4 低IF接收器。
3.5 直接轉換接收器中的問題。
3.5.1 雜訊。
3.5.2 LO洩漏和輻射。
3.5.3 相位和幅度不平衡。
3.5.4 直流偏移。
3.5.5 互調。
3.6 架構比較和權衡。
3.7 結論。
4 基於矽的接收器設計。
4.1 接收器架構和設計。
4.1.1 系統描述和計算。
4.1.2 OFDM基礎。
4.1.3 系統架構。
