FSM-based Digital Design using Verilog HDL (Hardcover) (基於FSM的數位設計:使用Verilog HDL)

Peter Minns, Ian Elliott

  • 出版商: Wiley
  • 出版日期: 2008-05-01
  • 售價: $6,320
  • 貴賓價: 9.5$6,004
  • 語言: 英文
  • 頁數: 408
  • 裝訂: Hardcover
  • ISBN: 0470060700
  • ISBN-13: 9780470060704
  • 相關分類: Verilog
  • 海外代購書籍(需單獨結帳)

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商品描述

As digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic than their alternatives, leading to the development of faster digital hardware systems. 

This clear and logical book presents a range of novel techniques for the rapid and reliable design of digital systems using FSMs, detailing exactly how and where they can be implemented.   With a practical approach, it covers synchronous and asynchronous FSMs in the design of both simple and complex systems, and Petri-Net design techniques for sequential/parallel control systems. Chapters on Hardware Description Language cover the widely-used and powerful Verilog HDL in sufficient detail to facilitate the description and verification of FSMs, and FSM based systems, at both the gate and behavioural levels. 

Throughout, the text incorporates many real-world examples that demonstrate designs such as data acquisition, a memory tester, and passive serial data monitoring and detection, among others. A useful accompanying CD offers working Verilog software tools for the capture and simulation of design solutions. 

With a linear programmed learning format, this book works as a concise guide for the practising digital designer. This book will also be of importance to senior students and postgraduates of electronic engineering, who require design skills for the embedded systems market.

商品描述(中文翻譯)

隨著數位電路元件的尺寸減小,導致系統越來越複雜,一個能夠用於控制和設計各種半導體設備的基本邏輯模型變得至關重要。有限狀態機(FSM)具有許多優點;它們可以應用於許多領域(包括馬達控制、信號和串行數據識別等),並且它們使用的邏輯比其他替代方案少,從而促使更快速的數位硬體系統的發展。

這本清晰而邏輯的書介紹了一系列用於快速可靠地設計使用FSM的數位系統的新技術,詳細說明了它們可以如何以及在哪裡實施。以實用的方法,它涵蓋了在設計簡單和複雜系統時使用的同步和非同步FSM,以及用於順序/並行控制系統的Petri網設計技術。有關硬體描述語言的章節詳細介紹了廣泛使用且功能強大的Verilog HDL,以便在閘級和行為級別上描述和驗證FSM和基於FSM的系統。

整本書中融入了許多實際的例子,展示了數據收集、記憶體測試、被動串行數據監控和檢測等設計。附帶的有用光碟提供了用於捕獲和模擬設計解決方案的Verilog軟體工具。

這本書以線性程式化學習的形式,作為實踐數位設計師的簡明指南。這本書對於需要嵌入式系統市場的設計技能的高年級學生和電子工程研究生也非常重要。