Introduction to Microelectronics to Nanoelectronics: Design and Technology
Majumder, Manoj Kumar, Kumbhare, Vijay Rao, Japa, Aditya
- 出版商: CRC
- 出版日期: 2023-09-25
- 售價: $2,380
- 貴賓價: 9.5 折 $2,261
- 語言: 英文
- 頁數: 328
- 裝訂: Quality Paper - also called trade paper
- ISBN: 0367503247
- ISBN-13: 9780367503246
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相關分類:
微電子學 Microelectronics
海外代購書籍(需單獨結帳)
相關主題
商品描述
Focussing on micro- and nanoelectronics design and technology, this book provides thorough analysis and demonstration, starting from semiconductor devices to VLSI fabrication, designing (analog and digital), on-chip interconnect modeling culminating with emerging non-silicon/ nano devices. It gives detailed description of both theoretical as well as industry standard HSPICE, Verilog, Cadence simulation based real-time modeling approach with focus on fabrication of bulk and nano-devices. Each chapter of this proposed title starts with a brief introduction of the presented topic and ends with a summary indicating the futuristic aspect including practice questions. Aimed at researchers and senior undergraduate/graduate students in electrical and electronics engineering, microelectronics, nanoelectronics and nanotechnology, this book:
- Provides broad and comprehensive coverage from Microelectronics to Nanoelectronics including design in analog and digital electronics.
- Includes HDL, and VLSI design going into the nanoelectronics arena.
- Discusses devices, circuit analysis, design methodology, and real-time simulation based on industry standard HSPICE tool.
- Explores emerging devices such as FinFETs, Tunnel FETs (TFETs) and CNTFETs including their circuit co-designing.
- Covers real time illustration using industry standard Verilog, Cadence and Synopsys simulations.
商品描述(中文翻譯)
本書專注於微納電子設計和技術,從半導體器件到VLSI製造、模擬設計(模擬和數字)、片上連接建模,最終涵蓋新興的非矽/納米器件。它詳細描述了理論和行業標準HSPICE、Verilog、Cadence模擬的實時建模方法,重點關注大量和納米器件的製造。本書的每一章節都以簡要介紹所呈現的主題開始,並以總結結束,包括練習問題,並指出未來的方向。本書針對電氣電子工程、微電子學、納米電子學和納米技術的研究人員以及高年級本科生/研究生,提供廣泛而全面的覆蓋範圍,從微電子學到納米電子學,包括模擬設計在納米電子領域的應用。本書討論了器件、電路分析、設計方法和基於行業標準HSPICE工具的實時模擬。還探討了FinFET、Tunnel FET(TFET)和CNTFET等新興器件,包括它們的電路共同設計。並使用行業標準的Verilog、Cadence和Synopsys模擬進行實時演示。
作者簡介
Manoj Kumar Majumder received his PhD from Microelectronics and VLSI group at Indian Institute of Technology, Roorkee, India. Currently, he is working as assistant professor in Department of Electronics and Communication Engineering, IIIT Naya Raipur, Chhattisgarh. He has authored more than 25 papers in peer-reviewed international journals and more than 40 papers in international conferences. He has co-authored a book titled Carbon Nanotobe Based VLSI Interconnects-Analysis and Design (New York, NY, USA: Springer, 2014) and a book-chapter published by CRC Press. His current research interests include the area of graphene based Low power VLSI devices and circuits, On-chip VLSI interconnects and Through silicon vias. Dr. Majumder is associated with different academic and administrative activities of different positions in IIIT, Naya Raipur. He is an active member of IEEE, IEEE Electron Device Society and IEEE Circuits and Systems Society. He had delivered technical talks at different conferences in India and abroad. He is also an active reviewer of IEEE Transactions on electromagnetic Compatibility, IEEE Transactions on Nanotechnology, IEEE Electron Device Letters, Microelectronics Journal, IET Micro & Nano Letters, and other Springer Journals. He is a Member of many expert committees constituted by Government and Nongovernment organizations. He has also received many awards and recognitions from International Biographical Center, Cambridge, etc. His name has been listed in Marquis Who's Who in the World.
Vijay Rao Kumbhare received the B.Tech degree in Electronics and Telecommunication Engineering from National Institute of Technology, Raipur, India in 2008, and M.Tech degree with specialization of Telecommunication System Engineering (TSE) under Electronics and Engineering Communication Department from Indian Institute of Technology, Kharagpur, West Bengal, India, in 2011. He had worked experience as assistant professor more than 5 years. He is currently working toward the Ph.D degree from Dr. Shyama Prasad Mukherjee International Institute of Information Technology Naya Raipur, India. He has attended several workshop and conferences, along with an active reviewer of reputed IET Biotechnology. His current research interest are in the area of Graphene nanoribbon, Carbon nanotube and optical based On-chip VLSI interconnects, emerging nano-materials.
Aditya Japa received B.Tech. degree in Electronics and Communication Engineering from Sree Chaitanya College of Engineering, Karimnagar (J.N.T.U Hyderabad), Telangana, India, in 2012 and the M.Tech. degree in VLSI Design from Vignan's University, Andhra Pradesh, India, in 2015. He was a JRF under a DST project titled "Design, Analysis and Benchmarking of Energy efficient Hetero-junction tunnel FET based Digital, Analog and RF Building blocks during 2015-16. He is currently pursuing Ph.D. in Electronics and Communication Engineering from DSPM International Institute of Information Technology, Naya Raipur, India. His current research interest includes Hardware security subsystems like TRNG and PUF, emerging transistor technologies (Tunnel FETs), ultra-low power/energy efficient sensor readout circuits, VLSI design etc.
Brajesh Kumar Kaushik received his Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has extensively published in several national and international journals and conferences. He is a reviewer of many international journals belonging to various publishers including IEEE, IET, Elsevier, Springer, Taylor & Francis, Emerald, ETRI, and PIER. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and microelectronics such as International Journal of VLSI Design & Communication Systems (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; Journal of Electrical and Electronics Engineering Research (JEEER); and Academic Journals. He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Who's Who in Science and Engineering(R) and Marquis Who's Who in the World(R). Dr. Kaushik has been conferred with Distinguished Lecturer award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with a list of quality lectures in his research domain.
作者簡介(中文翻譯)
Manoj Kumar Majumder在印度羅爾基印度理工學院的微電子和VLSI組獲得博士學位。目前,他在印度IIIT Naya Raipur的電子與通信工程系擔任助理教授。他在同行評審的國際期刊上發表了超過25篇論文,並在國際會議上發表了超過40篇論文。他合著了一本名為《基於碳納米管的VLSI互連-分析與設計》(紐約,美國:Springer,2014)的書籍,並在CRC Press發表了一篇書章。他目前的研究興趣包括基於石墨烯的低功耗VLSI器件和電路、片上VLSI互連和矽通孔。Majumder博士參與了IIIT Naya Raipur的不同學術和行政活動。他是IEEE、IEEE電子器件學會和IEEE電路與系統學會的活躍成員。他在印度和國外的不同會議上發表了技術演講。他還是IEEE Transactions on electromagnetic Compatibility、IEEE Transactions on Nanotechnology、IEEE Electron Device Letters、Microelectronics Journal、IET Micro & Nano Letters和其他Springer期刊的活躍審稿人。他是政府和非政府組織組成的許多專家委員會的成員。他還從國際傳記中心、劍橋等地獲得了許多獎項和表彰。他的名字被列入了《世界名人錄》。
Vijay Rao Kumbhare於2008年從印度Raipur的國立技術學院獲得電子與通信工程學士學位,並於2011年從印度Kharagpur的印度理工學院的電子與通信工程系專業中獲得碩士學位。他擁有超過5年的助理教授工作經驗。他目前正在印度Naya Raipur的Dr. Shyama Prasad Mukherjee國際信息技術學院攻讀博士學位。他參加了多個研討會和會議,並是知名IET生物技術的活躍審稿人。他目前的研究興趣包括石墨烯納米帶、碳納米管和基於光學的片上VLSI互連、新興納米材料。
Aditya Japa於2012年從印度特蘭加納邦Karimnagar的Sree Chaitanya工程學院獲得電子與通信工程學士學位,並於2015年從印度安得拉邦的Vignan大學獲得VLSI設計碩士學位。他在2015-16年期間擔任了一個名為“能源高效異質結構隧道場效電晶體的數字、模擬和射頻基本組件的設計、分析和基準”的DST項目的JRF。他目前正在印度Naya Raipur的DSPM國際信息技術學院攻讀電子與通信工程博士學位。他目前的研究興趣包括硬件安全子系統(如TRNG和PUF)、新興晶體管技術(隧道場效電晶體)、超低功耗/能量高效的傳感器讀出電路、VLSI設計等。
Brajesh Kumar Kaushik於2007年從印度羅爾基印度理工學院獲得哲學博士學位。他於2009年加入印度理工學院羅爾基的電子與通信工程系擔任助理教授,自2014年4月起擔任副教授。他在多個國家和國際期刊和會議上廣泛發表。他是許多國際期刊的審稿人,包括IEEE、IET、Elsevier、Springer、Taylor & Francis、Emerald、ETRI和PIER。他曾擔任許多知名國際和國家會議的總主席、技術主席和主題演講嘉賓。Kaushik博士是IEEE的高級會員,也是IEEE的成員。