FireWire System Architecture: IEEE 1394a, 2/e
暫譯: FireWire 系統架構：IEEE 1394a，第 2 版

MindShare Inc., Don Anderson

FireWire System Architecture: IEEE 1394a, 2/e
  • 出版商: Addison Wesley
  • 出版日期: 1998-12-17
  • 售價: $882
  • 語言: 英文
  • 頁數: 544
  • 裝訂: Paperback
  • ISBN: 0201485354
  • ISBN-13: 9780201485356

    • 已絕版

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Table Of Contents

(Most chapters begin with an Overview.)
About This Book.

The MindShare Architecture Series
Cautionary Note.
Organization of This Book.
Part One: Introduction to FireWire (IEEE 1394).
Part Two: Serial Bus Communications.
Part Three: Serial Bus Configuration.
Part Four: Serial Bus Management.
Part Five: Registers and Configuration ROM.
Part Six: Power Management.
Appendix.
Target Audience.
Prerequisite Knowledge.
Documentation Conventions.
Labels for Multi-byte Blocks.
Hexadecimal Notation.
Binary Notation.
Decimal Notation.
Bit Versus Byte Notation.
Identification of Bit Fields (logical groups of bits or signals).
Visit Our Web Page.
We Want Your Feedback.

I. INTRODUCTION TO FIREWIRE (IEEE 1394a).


1. Why FireWire?
Motivations Behind FireWire Development.
Inexpensive Alternate to Parallel Buses.
Plug and Play Support.
Eliminate Host Processor/Memory Bottleneck.
High Speed Bus with Scalable Performance.
Support for Isochronous Applications.
BackPlane and Cable Environments.
Bus Bridge.
1394 Applications.
IEEE 1394 Refinements.
Primary Features.

2. Overview of the IEEE 1394 Architecture.
IEEE 1394 Overview.
Specifications and Related Documents.
IEEE 1394-1995 and the IEEE 1394a Supplement.
IEEE 1394.B.
Unit Architecture Specifications.
IEEE 1394 Topology.
Multiport Nodes and Repeaters.
Configuration.
Peer-To-Peer Transfers.
Device Bay.
The ISO/IEC 13213 Specification.
Node Architecture.
Address Space.
Transfers and Transactions.
Control and Status Registers (CSRs).
Configuration ROM.
Message Broadcast.
Interrupt Broadcast.
Automatic Configuration.

II. SERIAL BUS COMMUNICATIONS.


3. Communications Model.
Transfer Types.
Asynchronous.
Isochronous.
The Protocol Layers.
Bus Management Layer.
Transaction Layer.
Link Layer.
Physical Layer.
A Sample Asynchronous Transaction.
The Request.
The Response.
An Example Isochronous Transaction.

4. Communications Services.
Anatomy of Asynchronous Transactions.
The Request Subaction.
Response Subaction.
Anatomy of Isochronous Transactions.
Setting Up Isochronous Transactions.
Maintaining Synchronization.
Isochronous Transactions.
Isochronous Transaction Initiation & Reception.

5. Cables & Connectors.
Cable and Connector Types.
6-pin Connector (1394-1995).
Make First/Break Last Power Pins.
Optional 4-pin Connector (1394a supplement).
Positive Retention.
Cable Characteristics.
6-Conductor Cables.
4-Conductor Cables.
Device Bay.

6. The Electrical Interface.
Common Mode Signaling.
Differential Signaling.
Recognition of Device Attachment and Detachment.
IEEE 1394-1995 Device Attachment/Detachment.
IEEE 1394a Device Attachment/Detachment.
Bus Idle State.
The Port Interface.
Differential Signal Specifications.
Arbitration Signaling.
Line State Signaling (1, 0, and Z).
Line State Detection.
Reset Signaling.
Line States During Configuration.
Line States During Normal Arbitration.
Starting and Ending Packet Transmission.
Dribble Bits.
Port State Control.
Speed Signaling.
High Speed Devices Slowed Due to Topology.
Devices of Like Speed Directly Connected.
Speed Signaling Circuitry.
Data/Strobe Signaling.
NRZ Encoding.
Data-Strobe Encoding.
Gap Timing.
Cable Interface Timing Constants.
Suspend/Resume.
Cable Power.
Cable Power Requirements.
Power Class.
Power Distribution.
Bus Powered Nodes.

7. Arbitration.
Arbitration Signaling.
Arbitration Services.
Asynchronous Arbitration.
Fairness Interval.
The Acknowledge Packet and Immediate Arbitration Service.
Isochronous Arbitration.
Cycle Start and Priority Arbitration.
Combined Isochronous and Asynchronous Arbitration.
Cycle Start Skew.
1394a Arbitration Enhancements.
Acknowledge Accelerated Arbitration.
Fly-by Arbitration.
Acceleration Control.
Priority Arbitration Service.
Summary of Arbitration Types.

8. Asynchronous Packets.
Asynchronous Packets.
Data Size.
Write Packets.
Asynchronous Stream Packet.
Read Packets.
Lock Operations.
Lock Request Packet.
Lock Response Packet.
Response Codes.
Acknowledge Packet.
Asynchronous Transaction Summary.
Write Transactions.
Summary of Read and Lock Transactions.
Cycle Start Packet.

9. Isochronous Packet.
Stream Data Packet.
Isochronous Data Packet Size.
Isochronous Transaction Summary.

10. PHY Packet Format.
PHY Packet Format.
Self-ID Packets.
Self-ID Packet Zero.
Self-ID Packets One, Two, and Three (1394-1995).
Self-ID Packets One and Two (1394a).
Link-on Packet.
PHY Configuration Packet.
Force Root Node.
Gap Count Optimization.
Extended PHY Packets.
Ping Packet.
Remote Access Packet.
Remote Reply Packet.
Remote Command Packet.
Remote Confirmation Packet.
Resume Packet.

11. Link to PHY Interface.
The Interface Signals.
Sharing the Interface.
PHY Initiated Transfers.
Link Initiated Transfers.
Determining Transfer Rate Between Link and PHY.
Powering the Link.
Packet Transmission.
Link Issues Request.
Receiving Packets.
PHY Reports Status.
ARB_RESET_GAP.
SUBACTION_GAP.
BUS_RESET_START.
PHY_INTERRUPT.
Accelerated Arbitration Control.
Accessing the PHY Registers.
PHY Register Reads.
PHY Register Writes.
Electrical Isolation Between PHY and Link.

12. Transaction Retry.
Busy Retry.
The First Packet Transmission Attempt.
Single Phase Retry.
Dual Phase Retry.
Transactions Errors.
Packet Transmission Errors.
Packet Error Handling Summary.

III. SERIAL BUS CONFIGURATION.


13. Configuration Process.
Bus Initialization (Bus Reset).
Tree Identification (The Family Tree).
Self Identification.
Bus Management.

14. Bus Reset (Initialization).
Sources of Bus Reset.
Power Status Change.
Bus Reset Signaled by Attached Node.
Node Attachment or Removal.
MAX_ARB_STATE_TIME Expires.
Software Initiated Bus Reset.
Bus Reset Signaling.
Effects of Bus Reset.
Topology Information Cleared.
PHY Register Changes.
CSR Register Changes.
1394-1995 and Reset Runaway.
Problem One: The Reset Storm.
The 1394a Solution: Debounce Port Status Signal.
Problem Two: Recognition of Connection Change Not Symmetric.
The Solution: Slow Node Accepts Fast Node's Reset Signaling.
Problem Three: Reset Signaled During Packet.
Transmission.

15. Tree Identification.
Tree ID Signaling.
The Tree ID Process.
Leaf Nodes Try to Find Their Parents.
Parents Identify Their Children.
Three Example Scenarios.
Scenario One.
Leaf Nodes Signal Parent_Notify.
Branch Nodes Locate Their Parents.
Scenario Two.
Leaf Nodes Locate Their Parents.
Root Contention.
Scenario Three.
Force Root Delay.
Leaf Nodes Attempt to Locate Their Parents.
Branch Nodes Attempt to Locate Their Parents.
Looped Topology Detection.

16. Self Identification.
Self-Identification Signaling.
Physical ID Selection.
Second and Subsequent Physical ID Assignment.
Self-ID Packets.
Self-ID Packet Zero.
Self-ID Packets One and Two (1394a).
Who Uses the Self-ID Packet Information.

IV. SERIAL BUS MANAGEMENT.


17. Cycle Master.
Determining and Enabling the Cycle Master.
Cycle Start Packet.

18. Isochronous Resource Manager.
Determining the Isochronous Resource Manager.
Minimum Requirements of Isochronous Resource Managers.
Enabling the Cycle Master.
Resource Allocation Registers.
Channel Allocation.
Bus Bandwidth Allocation.
Reallocation of Isochronous Resources.
Power Management.

19. Bus Manager.
Determining the Bus Manager.
Power Management.
Power Management by Bus Manager Node.
Power Management by IRM Node.
The Topology Map.
Accessing the Topology Map.
Gap Count Optimization.
The Speed Map.
Accessing the Speed Map.
Bus Bandwidth Set-Aside.

20. Bus Management Services.
Serial Bus Control Requests.
Bus Reset Control Request.
Initialize Control Request.
Link-On Control Request.
Present Status.
PHY Configuration Request.
Serial Bus Control Confirmations.
Serial Bus Event Indication.

V. REGISTERS & ROM.


21. CSR Architecture.
Core Registers.
Effect of Reset on the CSRs.
State Register (State_Clear & State_Set).
Node_IDS Register.
Reset_Start Register.
Indirect_Address and Indirect_Data Registers.
Split_Timeout Register.
Argument, Test_Start, and Test_Status Registers.
Units_Base, Units_Bound, Memory_Base, and Memory_Bound Registers.
Interrupt_Target and Interrupt_Mask Registers.
Clock_Value, Clock_Tick_Period, Clock_Strobe_Arrived, and Clock_Info Registers.
Message_Request & Message_Response Registers.
Serial Bus Dependent Registers.
Cycle_Time & Bus_Time Registers.
Power_Fail_Imminent & Power_Source Registers.
Busy_Timeout Register.
Bus_Manager_ID Register.
Bandwidth_Available Register.
Channels_Available Register.
Maint_Control Register.
Maint_Utility Register.
Unit Registers.
Topology Map.
Speed Map.

22. PHY Registers.
1394-1995 PHY Register Map.
Port Status Registers.
PHY Configuration Packet.
1394a PHY Register Map.
Page Select.

23. Configuration ROM.
Minimal ROM Format.
General ROM Format.
Header Information.
Bus_Info_Block (1394-1995).
Bus Info Block (1394a).
Root_Directory.
Company ID Value Administration.

VI. POWER MANAGEMENT.


24. Introduction to Power Management.
Review of 1394-1995 Power-Related Issues.
Goals of the 1394a Power Extensions.

25. Cable Power Distribution.
Power Distribution.
Power Class Codes.
Power Providers.
Power Consumer.
Self-Powered Nodes (Non Power Providers).
Local Power Down Summary.

26. Suspend & Resume.
Suspending a Port.
Suspending Via the Suspend Command Packet.
Suspending Via RX_SUSPEND.
The BIAS Handshake.
Suspending Via Port Disable.
Port Suspend Via Unexpected Loss of Bias.
Resuming Full Operation.
Resuming Via Resume Packet.
Resuming Via Resume Port Command Packet.
Resuming Via Port Events.

27. Power State Management.
Power Management.
Power States.
New CSRs.
New ROM Entries.

Appendix: Example 1394 Chip Solutions.
Overview.
1394 in the PC.
TSB12LV22 / OHCI-Lynx.
Features.
Overview.
TSB41LV03.
Putting it all Together.
1394 in the Digital Camera.
TSB12LV31 - GPLynx.
TSB21LV03A.
Putting it all Together.
For More Information.

Appendix: Glossary.
Index. 0201485354T04062001


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商品描述(中文翻譯)

目錄

（大多數章節以概述開始。）
本書介紹
MindShare 架構系列
警告說明
本書組織
第一部分：FireWire（IEEE 1394）介紹
第二部分：串行總線通訊
第三部分：串行總線配置
第四部分：串行總線管理
第五部分：寄存器和配置 ROM
第六部分：電源管理
附錄
目標讀者
先備知識
文件慣例
多位元組區塊標籤
十六進位表示法
二進位表示法
十進位表示法
位元與位元組表示法
位元欄位識別（邏輯位元或信號組）
訪問我們的網頁
我們希望聽到您的反饋

I. FireWire（IEEE 1394a）介紹

1. 為什麼選擇 FireWire？
FireWire 開發背後的動機
便宜的平行總線替代方案
即插即用支持
消除主機處理器/記憶體瓶頸
高速度總線，具可擴展性能
支持等時應用
背板和電纜環境
總線橋接
1394 應用
IEEE 1394 的改進
主要特徵

2. IEEE 1394 架構概述
IEEE 1394 概述
規範和相關文件
IEEE 1394-1995 和 IEEE 1394a 補充
IEEE 1394.B
單元架構規範
IEEE 1394 拓撲
多端口節點和重複器
配置
對等傳輸
設備艙
ISO/IEC 13213 規範
節點架構
地址空間
傳輸和交易
控制和狀態寄存器（CSRs）
配置 ROM
消息廣播
中斷廣播
自動配置

II. 串行總線通訊

3. 通訊模型
傳輸類型
非同步
等時
協議層
總線管理層
交易層
鏈路層
物理層
一個示例非同步交易
請求
回應
一個示例等時交易

4. 通訊服務
非同步交易的解剖
請求子動作
回應子動作
等時交易的解剖
設置等時交易
維持同步
等時交易
等時交易的啟動與接收

5. 電纜與連接器
電纜和連接器類型
6針連接器（1394-1995）
使第一個/最後一個電源針
可選的4針連接器（1394a 補充）
正向保持
電纜特性
6導體電纜
4導體電纜
設備艙

6. 電氣介面
共模信號
差分信號
設備連接和斷開的識別
IEEE 1394-1995 設備連接/斷開
IEEE 1394a 設備連接/斷開
總線空閒狀態
端口介面
差分信號規範
仲裁信號
線狀態信號（1、0 和 Z）
線狀態檢測
重置信號
配置期間的線狀態
正常仲裁期間的線狀態
開始和結束封包傳輸
滴位
端口狀態控制
速度信號
因拓撲而減速的高速設備
相同速度的設備直接連接
速度信號電路
數據/時鐘信號
NRZ 編碼
數據-時鐘編碼
間隙定時
電纜介面定時常數
暫停/恢復
電纜電源
電纜電源要求
電源類別
電源分配
總線供電節點

7. 仲裁
仲裁信號
仲裁服務
非同步仲裁
公平性間隔
確認封包和即時仲裁服務
等時仲裁
循環開始和優先仲裁
結合等時和非同步仲裁
循環開始偏差
1394a 仲裁增強
確認加速仲裁
飛越仲裁
加速控制
優先仲裁服務
仲裁類型摘要

8. 非同步封包
非同步封包
數據大小
寫入封包
非同步流封包
讀取封包
鎖定操作
鎖定請求封包
鎖定回應封包
回應代碼
確認封包
非同步交易摘要
寫入交易
讀取和鎖定交易摘要
循環開始封包

9. 等時封包
流數據封包
等時數據封包大小
等時交易摘要

10. PHY 封包格式
PHY 封包格式
自我識別封包
自我識別封包零
自我識別封包一、二和三（1394-1995）
自我識別封包一和二（1394a）
鏈接啟動封包
PHY 配置封包
強制根節點
間隙計數優化
擴展 PHY 封包
Ping 封包
遠程訪問封包
遠程回應封包
遠程命令封包
遠程確認封包
恢復封包

11. 與 PHY 介面的連接
介面信號
共享介面
PHY 發起的傳輸
鏈接發起的傳輸
確定鏈接和 PHY 之間的傳輸速率
為鏈接供電
封包傳輸
鏈接問題請求
接收封包
PHY 報告狀態
ARB_RESET_GAP
SUBACTION_GAP
BUS_RESET_START
PHY_INTERRUPT
加速仲裁控制
訪問 PHY 寄存器
PHY 寄存器讀取
PHY 寄存器寫入
PHY 和鏈接之間的電氣隔離

12. 交易重試
忙碌重試
第一次封包傳輸嘗試
單相重試
雙相重試
交易錯誤
封包傳輸錯誤
封包錯誤處理摘要

III. 串行總線配置

13. 配置過程
總線初始化（總線重置）
樹識別（家族樹）
自我識別
總線管理

14. 總線重置（初始化）
總線重置的來源
電源狀態變更
附加節點發出的總線重置信號
節點附加或移除
MAX_ARB_STATE_TIME 到期
軟體發起的總線重置
總線重置信號
總線重置的影響
拓撲信息清除
PHY 寄存器變更
CSR 寄存器變更
1394-1995 和重置失控
問題一：重置風暴
1394a 解決方案：去彈跳端口狀態信號
問題二：連接變更識別不對稱
解決方案：慢節點接受快節點的重置信號
問題三：在封包傳輸期間發出重置信號

15. 樹識別
樹 ID 信號
樹 ID 過程
葉節點嘗試尋找其父節點
父節點識別其子節點
三個示例場景
場景一
葉節點發出 Parent_Notify 信號
分支節點定位其父節點
場景二
葉節點定位其父節點
根節點競爭
場景三
強制根延遲
葉節點嘗試定位其父節點
分支節點嘗試定位其父節點
循環拓撲檢測

16. 自我識別
自我識別信號
物理 ID 選擇
第二次及後續的物理 ID 分配
自我識別封包
自我識別封包零
自我識別封包一和二（1394a）
誰使用自我識別封包信息

IV. 串行總線管理

17. 循環主控
確定和啟用循環主控
循環開始封包

18. 等時資源管理器
確定等時資源管理器
等時資源管理器的最低要求
啟用循環主控
資源分配寄存器
通道分配
總線帶寬分配
等時資源的重新分配
電源管理

19. 總線管理器
確定總線管理器
電源管理
由總線管理器節點進行的電源管理
由 IRM 節點進行的電源管理
拓撲圖
訪問拓撲圖
間隙計數優化
速度圖
訪問速度圖
總線帶寬保留

20. 總線管理服務
串行總線控制請求
總線重置控制請求
初始化控制請求
鏈接啟動控制請求
當前狀態
PHY 配置請求
串行總線控制確認
串行總線事件指示

V. 寄存器與 ROM

21. CSR 架構
核心寄存器
重置對 CSR 的影響
狀態寄存器（State_Clear 和 State_Set）
Node_IDS 寄存器
Reset_Start 寄存器
間接地址和間接數據寄存器
Split_Timeout 寄存器
參數、Test_Start 和 Test_Status 寄存器
Units_Base、Units_Bound、Memory_Base 和 Memory_Bound 寄存器
中斷目標和中斷遮罩寄存器
Clock_Value、Clock_Tick_Period、Clock_Strobe_Arrived 和 Clock_Info 寄存器
Message_Request 和 Message_Response 寄存器
串行總線依賴寄存器
Cycle_Time 和 Bus_Time 寄存器
Power_Fail_Imminent 和 Power_Source 寄存器
Busy_Timeout 寄存器
Bus_Manager_ID 寄存器
Bandwidth_Available 寄存器
Channels_Available 寄存器
Maint_Control 寄存器
Maint_Utility 寄存器
單元寄存器
拓撲圖
速度圖

22. PHY 寄存器
1394-1995 PHY 寄存器圖
端口狀態寄存器
PHY 配置封包

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